Control of DVR using enhanced transfer delay frequency-locked loop using sine–cosine optimization

The paper treats a dynamic voltage restorer (DVR) to nullify for problems related to voltage, like harmonics, swell, unbalance, and sag that can cause significant damage to sensitive electrical equipment. The fundamental components are extracted using an enhanced transfer delay frequency-locked-loop (ETD-FLL). The ETD-FLL has benefits such as high accuracy, low jitter, quick acquisition time, operating range is wider, power consumption is low, robustness for noise, flexibility in design, reduced sensitivity to component variations, and adaptability to digital control for a wide range of frequency synthesis and control applications. The ETD-FLL control algorithm typically uses two proportional–integral (PI) controllers to control the DVR output. The first controller (PI) is responsible for regulating the DVR’s DC bus voltage, while the second controller (PI) is applied to adjust the DVR reactive power output. Proper selection of the PI gains can help ensure the efficient and stable operation. The sine–cosine optimization is simple to implement, with faster convergence, good exploration–exploitation balance, robustness, fewer parameters to tune ,and versatility than traditional optimization algorithms for extracting PI gains. The ETD FLL is validated by close tracking of load voltage and reference load voltage during transients. The optimization technique based on sine–cosine algorithm (SCA) decreases overshoot to 26%, rising time to 0.15 s, and settling time to 1.10 s with manual tuning. With 1% overshoot, 0.05 s rise time, and 0.92 s settling time, manual tuning excels at terminal voltage. SCA-optimized PI gains maintain AC terminal voltage performance with 1.2% overshoot, 0.2 s rise time, and 0.85 s settling time. These findings, validated by voltage waveforms, demonstrate SCA's efficacy in enhancing control responses. The simulation results are validated by the hardware prototype using the d-SPACE MicroLab box.