A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing

During the last decades, CMOS technology miniaturized according to Moore’s law, which predicted that the number of transistors per silicon chip doubles every two years [27]. However, its continuation became challenging, due to limitations on the transistor miniaturization and the increasing demand for emerging applications requiring high-performance systems with strict constraints, posing significant challenges to device technologies and computer architectures [18]. Regarding device technology, reliability, leakage, and cost are the identified walls [18]. Moreover, the memory, power, and Instruction Level Parallelism (ILP) walls are affecting computer architectures [18]. Memristive devices represent one of the most promising candidates to complement CMOS technology, or replace it, in certain applications such as Flash memory, mainly due to their CMOS manufacturing process compatibility, zero standby power consumption, as well as high scalability and density [6, 18, 26]. In addition, these devices can be used not only as memory but also as computing elements [18]. Memristive devices can be classified according to different criteria, such as the dominant physical switching mechanism. In this context, one of the most versatile types is the Redox-based one. In more detail, this kind of memristive device can be used for implementing Redox-based Resistive Random Access Memory (ReRAM). Note that ReRAMs are classified as non-volatile memory [2, 21, 32].

However, the use of these devices depends on being able to guarantee their quality after manufacturing as well as reliability during their lifetime. Despite the lack of information regarding realistic manufacturing deviations, literature already describes that ReRAMs can be affected by unique faults [14, 19, 20], consequently demanding the development of new manufacturing test procedures [15, 16].

In [28], the authors provide a review of the memristive device manufacturing process and a discussion related to possible defects that may affect these novel devices, identifying the relation between manufacturing failure mechanisms and faulty behaviors. In addition, in the last few years, some new manufacturing test strategies were proposed in literature, since traditional March Tests, which explore the execution of predefined read and write operations applied at each ReRAM cell, are extremely time-consuming and further not able to guarantee the detection of all unique faults. In the following, some test strategies for manufacturing testing are presented. When considering strategies targeting passive crossbars, a scheme based on “sneak-path sensing” able to test multiple elements of Phase Change Memories at the same time was presented in [23]. The detection is based on a comparison between the output current related to a specific group of cells and the ideal current, accessed based on the execution of March elements. The main drawbacks are that it only works for ReRAMs that have sneak-paths as well as its limitation in terms of cells that can be tested in parallel. In [25], a review of the fault model related to 1R crossbars is presented. In addition, this work presents a March RC with new read operations and a DfT architecture. When considering 1T1R-based ReRAMs, in [19], two DfT schemes that exploit the access time duration and supply voltage level of ReRAM cells to facilitate the detection of unique faults were described. The main drawbacks of these techniques are the test time and the implementation effort required to guarantee high fault detection capability. Finally, in [30], low-cost DfT solutions that augment the testing process and improve the fault coverage of RRAMs are presented. In more detail, a Computation-in-Memory (CiM) based DfT is realized to expedite the detection and diagnosis of faults. Moreover, reconfigurable logic designs (programmable reference generations, period, and voltage of operation) are developed to detect unique RRAM faults.

In this context, this paper presents an extension of the work originally described in [9, 10], which despite being able to provide the required fault detection capability with respect to unique faults, introduced significant area and power overheads to the ReRAM as well as was significantly affected by process variation. In more detail, the main contributions of this paper are:

It is important to note that this paper adopts a ReRAM composed of 1T1R (1 Transistor and 1 Memristor) cells, where the 1R is Bipolar-, Valence Change Mechanism (VCM)-based filamentary device.

The remainder of this paper is structured as follows. Section 2 presents the background related to ReRAMs, fault models, and defect injection schemes. Section 3 summarizes the strategy presented in [10] and describes the optimized DfT strategy based from [9]. In Section 4 the experimental setup is described and Section 5 summarizes the obtained results including a discussion about overheads and process variation impact. Finally, in Section 6 we conclude the paper.

This Section introduces the main concepts regarding ReRAMs and summarizes the existing fault models as well as the defect injection schemes that can be adopted for modeling possible manufacturing defects.

In the following will be presented the original DfT Strategy published in [10], then the Optimized DfT Strategy that will be explored in the rest of the paper.

In order to validate the optimized DfT strategy and demonstrate its fault detection capability, a case study composed of a 3x3 word-based ReRAM, where each word is composed of 3 ReRAM cells, including peripheral circuitry, was adopted. The case study and the DfT Circuitry were implemented using a 130 nm Predictive Technology Model (PTM) for the CMOS-based circuits and the ReRAM (Pt/HfO₂/TiO_x/Pt) compact model proposed in [2, 11]. Figure 6 shows the block diagram of the adopted case study including the DfT circuitry. Regarding the adopted implementation granularity, all words (Word00, Word10, and Word20, for example) present in the same column share the same DfT circuitry. In addition, all words (Word00, Word01, and Word02, for example) on one row share the Word Line (WL) and the Select Line (SL), while all words in one column share the Bit Line (BL). As previously mentioned every word consists of three 1T1R ReRAM cells, storing one bit of data, see Fig. 5(a). Each BL and SL is connected to a capacitance of 150 fF, emulating a larger ReRAM for more realistic simulation results. The peripheral circuitry implements the Read-and-Write Logic. The Column-Address-Decoder selects the desired column, Column Select (CS). Similarly, the WL-Decoder selects the WL that corresponds to the desired row address, once the WL enable (WL_EN) signal is set. BL and SL Drivers act to allow write and read operations on the block, varying its voltage accordingly with the target operation. Note that when a write operation (write ‘0’ or write ‘1’) is performed, a RESET operation is performed first on the selected word. This RESET operation is performed by driving the SL to V_reset and the corresponding BL to Gnd. When the data to be written is a ‘1’, a SET operation is performed subsequently on that cell only. This is done by setting the BL to V_SET and the SL to Gnd. This writing scheme ensures that the cells are not over-SET, which may lead to low reliability [1]. For the read operation, it uses the Sense Amplifiers connected to the BLs, given a Data_Out for each bit line. Also, the DfT Circuitry is implemented in this point, generating the output signals DfT_Circuitry_Outs (DfT_DH, DfT_DL, and DfT_U) for each column, please check the explanation provided in Section 3.2. Finally, the adopted voltage for performing a write ‘1’ operation, or in other words a SET operation, is equal to 1.6 V, which is the nominal voltage adopted in the entire circuit. The RESET operation (write ‘0’) is performed by applying a voltage of \(-\)1.7 V. Usually, a higher RESET voltage is adopted in order to minimize the required operation time. The room temperature used in this experiment was 27 °C.

It is important to point out that in this work, the faulty behavior of ReRAM cells was introduced by adopting the DO model based on the approach described in [13, 15, 16]. This model incorporates the impact of physical defects on the device’s technology parameters and thereafter on its electrical parameters. In more detail, the defects were modeled by changing the values related to the oxygen vacancy concentration in the disk of the memristive device (N_real) according to [11]. By increasing the lowest possible concentration of oxygen vacancies (N_disc,min) the maximum resistance in the HRS is lowered because the current that can flow through the device is higher with a higher N_disc,min. The same principle is used but in an opposite way, when the highest possible concentration of oxygen vacancies in the disk (N_disc,max) is decreased, then the minimum resistance in LRS is increased. The current flowing through the device will decrease leading to higher resistance in LRS. This method makes the simulation of a device in an undefined state possible while keeping its memristive device-like behavior. Note that N_real, N_disc,min and N_disc,max are parameter names used in the JART model v1b [11], being measured in m\(^{-3}\) [2, 11].

The detection capability of the proposed DfT strategy was evaluated through electrical simulations using Spectre (Cadence). The defects were injected using the DO model, where N_disc,min and N_disc,max values were modified to change the ReRAM cell resistive state in order to indicate all possible unique faults: the extreme HRS (DeepF High), the undefined state (UWF), and the extreme LRS (DeepF Low). For this work, the LRS is defined to be represented by a resistance in the range of 1.75 k\(\Omega\), and 10 k\(\Omega\). The HRS is defined to assume a value between 53.2 k\(\Omega\), and 110 k\(\Omega\). Thus, the undefined state is represented by resistance values between 10 k\(\Omega\) and 53 k\(\Omega\). The extreme HRS is set to assume values above 111 k\(\Omega\), and, finally, the extreme LRS assumes values below 1.74 k\(\Omega\). These limits are represented by the N_real parameter that is limited by N_disc,min and N_disc,max parameters [11]. Table  1 summarizes the values of N_real parameter adopted to represent extreme HRS, HRS, undefined (‘U’) state, LRS, and extreme LRS in the ReRAM cell. Table 1 also includes the range of resistance value equivalent to each N_real value adopted for indicating all five possible states. When it is intended to simulate a unique fault, the N_disc,max and N_disc,min parameters are modified to the Upper and Lower Limit according to Table 1. Observing Table  1 it is possible to see that the variation of N_real is not linear when compared with the resistance value. Note that a variation of 0.007\(\times 10^{26}\) m\(^{-3}\), starting from 0.008\(\times 10^{26}\) m\(^{-3}\), is enough to cause a resistance variation from 110 k\(\Omega\) to 53.2 k\(\Omega\). To resume, a small variation in the N_disc,min value makes the device not able to switch to HRS. A complete study about the impact of electrical parameters variation on the memristive device behavior can be found in [3].

The next four figures demonstrate the detection capability of the proposed approach with respect to the detection of UWF, URF, and DeepFs. In more detail, the figures show the comparison between defective and defect-free ReRAM cells while performing a pre-defined operating sequence. The ReRAM cell’s resistance, the BL and SL’s voltage over the cell, the WL’s voltage as well as Data_Out and the DfT Outputs are presented. Figure 7(a) shows the detection of a UWF while performing the following operating sequence 0w1r1. In addition, the graph also demonstrates the operating behavior of the adopted 3x3 word-based ReRAM, where first a RESET operation is performed, by an active SL signal, then BL is activated making the SET operation (it should be inactive for write ‘0’), and the WL is active during the whole write operation, then it is briefly active during the READ. Also, the graph shows that the defective ReRAM cell assumes a resistance value of 18.8 k\(\Omega\), while the defect-free cell is at 2.64 k\(\Omega\). Note that the resistance value’s axis is represented using a logarithm scale to provide a better visualization). The Data_Out signal from both cases is a logical ‘1’, however, the DfT_U signal detects the ‘U’ state of the defective cell. Figure 7(b) depicts the detection of a UWF while performing a READ ‘0’ operation, where the defective ReRAM cell has a resistance value of 46.9 k\(\Omega\) after the write ‘0’ operation. If considering only the read operation for the test analysis, it can be said that the circuit is detecting a URF.

In Fig. 8, the detection of DeepFs is depicted. Figure 8(a) shows the detection of a Deep Low Fault (DfT_DL). Note that the defective ReRAM cell assumes the resistance value of 1.67 k\(\Omega\) after the SET operation. In addition, the High Deep Fault detection depicted in Fig. 8(b), DfT_DH signal, shows the fault detection when the ReRAM cell assumes a value of 113 k\(\Omega\). The Data_Out for both cases indicates a correct logic value, demonstrating the parametric nature of DeepFs. Note that this specific type of fault changes the resistive state of the memristive device to levels above the nominal ones. This situation makes the device more resilient to transition resistance during the write operation, for example.

After evaluating the fault detection capability of the optimized DfT strategy, a further evaluation considering the impact of process variation on the resolution of the DfT circuitry was performed. For this purpose, Monte Carlo (MC) simulations were performed in the DfT circuitry. In more detail, channel length and width as well as oxide thickness were varied adopting a 3\(\sigma\) Gaussian distribution with a variation of 4% inter-die. Table 2 presents the percentage of incorrect detection, considering all unique faulty behaviors. A total of 1000 simulations for each unique fault were performed. The obtained results show that the DfT circuitry had only 4.0% of False Positive Detection when considering Deep High faults, and 3.8% of False Positive Detection for Deep Low faults. Note that no False Positive Detection was observed for UWFs. In addition, when considering defective ReRAM cells, the DfT circuitry was not able to properly detect Deep High faults in 4.3% of the 1000 simulations, Deep Low faults in 0.3% as well as UWFs in 3.1%, when executing 1w0r0 (read ‘0’), and in 1.1% when performing 0w1r1 (read ‘1’). A further analysis of the possible false positive’s causes was conducted and the conclusion was that the circuits that implement the reference voltages are considerably affected by process variation. An alternative implementation for the reference voltage’s circuits is being currently investigated. One possible solution based on the use of a read circuit that can adjust the used reference voltage can be found in [7]. It is important to comment, that in the work published in [10], the evaluation of the process variation impact was performed assuming the reference voltages as constant sources.

Regarding the introduced overheads, the power consumption overhead in this case study is around 9% when the proposed DfT circuitry is added, considering that the implementation granularity is one DfT circuitry per BL. Table 3 presents the average power consumption related to the optimized DfT strategy compared with the write operations of one ReRAM cell. The DfT strategy power consumption is estimated at around 8.3 µW during the read operation, which is not so relevant when compared to the average power consumption of a ReRAM cell, of 79.2 µW during the write ‘0’, and 610.8 µW during the write ‘1’ operation. It is interesting to notice, that the power consumption is higher during the SET stage due to the increase in conductivity of the ReRAM cell. Note that by shortening the SET operation time this power consumption can be reduced.

Considering the area overhead, when compared with the previously published work [10], the optimized DfT strategy has a reduction of 25% in the number of transistors, since the transistors required for the implementation of the previous AMP are not required anymore. Finally, the implementation granularity of the DfT strategy plays an important role related to overheads and consequently, different schemes can even further minimize the overheads. Another important aspect is that the proposed DfT strategy could be optimized in order to also be used during a lifetime to provide detection of in-field faults, increasing the reliability of ReRAMs.

In relation to the technology detection capability, Table 4 gives an overview of it. The methodology was developed to detect the unique states of memristor, which are HtD but can also detect easy-to-detect (EtD) faults as transition and stuck-at faults. For ReRAM architectures that use pulses of write and read for verification, the DfT can be active during the verification to detect the UWFs. The URFs and DeepFs can be detected during a normal read operation. For intermittent faults, it cannot be determined with only one operation.

This paper proposes an optimization of the DfT Strategy presented in [10] for performing high-volume manufacturing testing of ReRAMs. The proposed strategy is based on the introduction of a DfT circuitry able to provide the detection of unique faults in ReRAM cells. In more detail, the DfT circuitry measures the current that flows through the 1T1R ReRAM cells and compares the read value with four reference values. The strategy was validated using a case study composed of a 3x3 word array, where each word includes 3 1T1R ReRAM cells, including peripheral circuitry. The obtained results demonstrated that the DfT circuitry is able to provide the detection of unique faults associated to possible defects that can be introduced during manufacturing. Simulations also demonstrated that the optimized DfT strategy can better tolerate the impact of process variation when compared to the strategy presented in [10]. In addition, the proposed optimization was able to reduce the introduced area overhead by 25% and increase the power consumption by 9%. Note that the introduction of a variable reference voltage could also be an interesting solution for reducing the strategy’s area overhead. As a future work, we intend to explore the DfT circuitry to also perform in-field on-line testing to improve ReRAM’s reliability during its lifetime.